1. Field of the Invention
This invention relates generally to interconnection of multiple electrical devices, and more particularly to interconnection of multiple ASIC devices, for example, multiple Field Programmable Gate Array (FPGA) devices.
2. Description of the Related Art
In the past, multiple FPGA devices have been interconnected as an array on a single circuit card using point-to-point or bussed parallel wiring configurations. Such configurations use many wires (along with associated I/O counts and termination components) to achieve required data transfer bandwidths, thus requiring the creation of many connection layers on a circuit card leading to undesirable outcomes such as a high degree of mechanical complexity and cost. Examples of these parallel interfaces include those using signaling standards such as Gunning Transceiver Logic (“GTL”), Stub-Series Termination Logic (“SSTL”), and High-Speed Transceiver Logic (“HSTL”). Some of these standards require as many as three termination components per signal to implement.
Additional parallel wiring is typically employed when a FPGA array is used to implement multiple card-level interfaces and embedded processor nodes, further increasing circuit complexity. In addition, diverse types of interfaces (VME64x, Race++, and PCI), processors and user hardware modules are often required to communicate with each other on a single card, further complicating inter-card communications issues. For example, current commercial products commonly bridge two standard interfaces together, such as VERSA-Module Europe (“VME”) and Peripheral Component Interconnect (“PCI”) interfaces using parallel bridging chips. Additionally, system-level FPGAs with embedded Power PC (“PPC”) or similar functions require implementation of more processing and interface nodes on a single card. Banking of I/O pins has reduced the need for termination components, but large I/O counts still require many layers to route, driving printed circuit board (“PCB”) layer counts and costs upward.
In addition to parallel wiring configurations, FPGAs on a single card have been interconnected using IEEE 1149 (Joint Test Action Group—“JTAG”) serial interconnections for configuration purposes. However, such JTAG serial interconnections are not suitable for functions such as high-speed data transfer or signal processing. Thus, the use of multiple large FPGAs, embedded processors, and various standard interfaces on a single card present significant problems with card layout/routing and inter-card communication.